Office Phone No.: 03228-250972, Extn - 1509

Residential Phone No.: 9434418112

Personal Phone No.: 6296990293

Quarter No: C-40/3, KTPP Township, Purba Medinipur

 Ph. D from  IIT, Kharagpur in  E & ECE in the year of 2015

 M. E. from  Jadavpur University in  Computer Science and Engineering in the year of 1998 with  1st Class.

 B. Tech. from  Calcutta University in  Computer Science and Engineering in the year of 1996 with  1st Class.

 B. Sc. from  Calcutta University in  Physics (Hons) in the year of 1992 with  1st Class.

 Assistant Professor,  CEM Kolaghat,  06/09/2003 to till date.

 Lecturer,  CEM Kolaghat,  30/07/1999 to 05/09/2003.

 Lecturer, Ad-hoc,  BPCIT, Krishnagar,  16/12/1997 to 29/07/1999.

 Don’t care filling to Reduce Leakage Power in VLSI Circuit Testing from  T. K. Maiti and S. Chattopadhyay,  8th IEEE Workshop on RTL and High Level Testing (WRTLT07), Beijing, China, Oct 12-13, 2007, pp 139-144. in  2007.

 Don’t care filling for power minimization in VLSI circuit testing from  T. K. Maiti and S. Chattopadhyay,  IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, USA, May 18-21, 2008, pp 2637-2640 in  2008.

 Input Assignment Technique for Low Power Circuit Testing from  Subhadip Kundu, Kanchan Manna, T. K. Maiti and S. Chattopadhyay,  12th IEEE VLSI Design and Test Symposium (VDAT2008), Bangalore, India, July 23-26, pp 189-196. in  2008.

 Confidence Based Power Aware Testing from  Subhadip Kundu, Kanchan Manna, T. K. Maiti and S. Chattopadhyay,  3rd International Symposium on Electronic system Design (ISED), BESU, Shibpur (Kolkata), WB, India, Dec 19-22. in  2012

 Present IT Scenario Organized by  Dept. of CSE, RE College, Durgapur, during  18/12/1999 – 19/12/1999.

• State Level Seminar on “Present IT Scenario”, Dept. of CSE, RE College, Durgapur, from 18/12/1999 – 19/12/1999
• Seminar on “Multimedia for IT Enabled Education”, held at SET, Dept. of Education Technology, JU, Kolkata in 2000.
• Workshop on “Bioinformatics and its Application”, Dept. of Biotech, IIT, KGP, Sept. 26-27, 2003
• National Seminar on “Applying Creativity and Systems Thinking for Business Innovation”, Hotel Taj Bengal, Kolkata, April 23-24, 2004, organized by Computer Engineering Division, WBSC, The Institute of Engineers (India).
• Invited Speech on “Global Initiative on Workforce Development and vision of IBM IT Education Services”, Park Hotel, Kolkata, 30^th April, 2004.
• In-house Workshop on “Design and Fabrication of Printed Circuit Board (PCB)”, Process Control Laboratory, Dept of ECE & EIE, CEM, Kolaghat, July 27-30, 2004.
• Training Program on “Rational Rose Suit of IBM”, Multimedia Laboratory, Dept of CSE & IT, CEM, Kolaghat, November 6-7, 2004.
• Orientation/Refresher Course on “VLSI Design & Testing”, Dept of CSE, Jadavpur University Campus, October 17-November 05, 2005.
• Two-day Workshop on “Quality Enhancement of Engineering Education through NPTEL”, organized by Center for Education Technology, IIT, Kharagpur (at CET), March 27-28, 2006.
  Subject taken at Undergraduate Level

  ¶ PDCA Course (BPCIT, Nadia) » C and FORTRAN Programming, Digital Electronics, Computer Organization, System Software, Discrete Structure, Graph Theory, Microprocessor and Computer Network. ¶ MCA Couse (Vidyasagar Univ) » Computer Organization and Architecture. ¶ BE (Hons) Course (CEMK, VU) » Computer Basic, Introduction to Programming (Pascal & C), Data Structure, Object Oriented Programming, Graph Theory, Switching and Automata Theory, Software Engineering, Computer Organization & Architecture, Principles of Language Translator, Microprocessor & Applications, Peripheral Devices& Interfaces, Parallel & Distributed Computing and VLSI Design. ¶ B.Tech Course (CEMK, WBUT) » Introduction to Computing, Programming for Problem Solving, Data Structure & Algorithm, Formal Language & Automata Theory, Computer Organization & Architecture, Advanced Architecture, Language Translator,Computer Networks, Inter-networking, Distributed Computing and Personality Development.

  Area of Specializations/Research Areas

  Power Minimization in VLSI Testing